Articles tagged with "Transistors, Nanotechnology, Semiconductors"

Intel details progress on fabbing 2D transistors a few atoms thick in standard high volume fab production environment — chipmaker outlines 300-mm fab compatible with integration of 2D transistor contacts and gate stacks

Intel Foundry and imec have made progress in integrating 2D transistors into standard high-volume fab production environments, demonstrating a 300-mm fab compatible with 2D transistor contacts and gate stacks. The industry is moving towards 2D materials like transition-metal dichalcogenides (TMDs) to address limitations in silicon channels due to scaling. Intel's innovative contact and gate-stack integration scheme aims to overcome challenges in developing 2D field-effect transistors (2DFETs) for future chip production. This work aims to de-risk the development of chips relying on 2D materials and accelerate device benchmarking and design exploration. Intel's strategy involves early collaboration with partners like imec to address manufacturing challenges associated with 2D materials before they become necessary.

Tom's Hardware•

5 months ago

SemiEngineering

Research Bits: Oct. 7

Researchers have developed a new technique called modulation acceptor doping (MAD) to improve the conductivity of silicon-germanium (SiGe) transistors by doping the insulating oxide layer. This approach could lead to more efficient nanotransistors with lower energy consumption. Another study revealed how atoms in semiconductors arrange themselves in distinctive patterns that impact the material's band gap, potentially enabling advancements in information technology at the atomic scale. Additionally, a team from the National Renewable Energy Laboratory created a silicon-carbide-based power module with higher energy density and lower parasitic inductance, suitable for various applications like data centers and electric aircraft.

SemiEngineering•

7 months ago

Scaling Nanoribbon Transistors Based on Monolayer 2D Semioconductors (Stanford, HORIBA, SLAC)

Researchers from Stanford University, HORIBA Scientific, and SLAC National Accelerator Laboratory published a technical paper on scaling nanoribbon transistors using monolayer transition metal dichalcogenides. The paper discusses the fabrication of nanoribbon transistors with channel widths down to 25 nm and lengths down to 50 nm, achieving high on-state currents for both n- and p-type devices. The use of monolayer 2D semiconductors in nanoribbon transistors shows promise for future nanosheet transistor applications. The research demonstrates advancements in scaling down transistor dimensions while maintaining good performance.