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TSMC SoIC 3D stacking roadmap outlines path from 6-micron pitches today to 4.5-micron in 2029 — Fujitsu's Monaka CPU to benefit from face-to-face chiplet stacking

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Tom's Hardware

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TSMC is advancing its System on Integrated Chips (SoIC) technology with 3D stacking, moving from 6-micron pitches in 2025 to 4.5-micron by 2029. Face-to-face (F2F) chiplet stacking, supported by 2nd generation SoIC, is crucial for improved performance, bandwidth, and energy efficiency. Companies like Broadcom are utilizing this technology for Fujitsu's Monaka CPU, featuring Armv9 cores and hybrid copper bonding for enhanced cache and single-thread performance. While some caution is observed in adopting the latest 3D integration technologies, TSMC is accelerating its stacking timelines to enable customers to stack advanced dies sooner, positioning SoIC 3D stacking as a key solution for increasing compute density in the face of slowing transistor scaling.

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