Catching Critical Defects In TSVs And Stacked Chips

The article discusses the challenges in identifying critical defects in through-silicon vias (TSVs) and stacked chips due to high process variation in advanced packaging architectures. The use of AI is highlighted as a solution to distinguish between yield-killing and nuisance variations, reducing false positives. Various inspection methods, such as optical/IR, electron beam, X-ray, and acoustic modalities, are being employed to test TSV structures non-destructively. The article emphasizes the importance of new tools and technologies in detecting defects in 2.5D and 3D multi-chiplet assemblies to ensure long-term reliability and performance.