Articles tagged with "DRAM, Memory, Optimization"

The Impact Of DRAM Writes On DDR5-Based Systems (Georgia Tech)

Georgia Tech published a technical paper titled "BARD: Reducing Write Latency of DDR5 Memory by Exploiting Bank-Parallelism." The paper explores the impact of DRAM writes on DDR5-based systems and introduces a method to reduce write latency by favoring lower-latency write requests. The proposed approach, BARD (Bank-Aware Replacement Decisions), modifies cache replacement policies to increase bank-parallelism of DRAM writes. Evaluations across various workloads show that BARD-H improves performance by an average of 4.3% and up to 8.5%, requiring only 8 bytes of SRAM per LLC slice.