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The Impact Of DRAM Writes On DDR5-Based Systems (Georgia Tech)

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SemiEngineering

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Georgia Tech published a technical paper titled "BARD: Reducing Write Latency of DDR5 Memory by Exploiting Bank-Parallelism." The paper explores the impact of DRAM writes on DDR5-based systems and introduces a method to reduce write latency by favoring lower-latency write requests. The proposed approach, BARD (Bank-Aware Replacement Decisions), modifies cache replacement policies to increase bank-parallelism of DRAM writes. Evaluations across various workloads show that BARD-H improves performance by an average of 4.3% and up to 8.5%, requiring only 8 bytes of SRAM per LLC slice.

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