Tech News
Back to home
Technology

Transforming Functional Verification through Intelligence

Source

SemiWiki

Published

TL;DR

AI Generated

Siemens is introducing Questa One, an intelligent verification tool to address the challenges faced by SoC projects running behind schedule due to increased complexity. Questa One offers a unified approach to verification, utilizing real-time analytics and automated regression management to improve efficiency. The tool's Unified Coverage Database (UCDB) merges various coverage metrics and enables collaborative features, reducing closure times and freeing up engineering hours. Additionally, Questa One's Sim Coverage Acceleration (QCX) accelerates coverage from 80% to 100% by analyzing the landscape and generating targeted tests, resulting in up to 100x faster closure time. This comprehensive tool suite aims to transform verification into a more adaptive and optimized process.

Read Full Article

Similar Articles

Solving the EDA tool fragmentation crisis

Solving the EDA tool fragmentation crisis

Design teams are facing challenges with EDA tool fragmentation as specialized tools for IC verification struggle to share design data efficiently. The Calibre Connectivity Interface (CCI) aims to bridge this gap by transforming Layout vs. Schematic (LVS) verification data into a universal source that downstream tools can access accurately. CCI operates on the Standard Verification Database (SVDB) to provide rich connectivity data for various analysis tools, including parasitic extraction, electromagnetic simulation, and power integrity analysis. Integration with third-party tools like Empyrean's PEX, Phlexing's GloryEX, Synopsys StarRC, and Cadence QRC showcases CCI's ability to streamline workflows and enhance design accuracy. The article emphasizes the importance of seamless multi-tool integration in modern IC design to improve efficiency and accelerate time-to-market for semiconductor innovation.

SemiWiki•
How to Overcome the Advanced Node Physical Verification Bottleneck

How to Overcome the Advanced Node Physical Verification Bottleneck

Advanced semiconductor process technology poses challenges in physical verification, the final gate to manufacturing. With shrinking process nodes, the number of checks has quadrupled, leading to bottlenecks in full-chip runs that can take days to weeks. Synopsys IC Validator offers a solution with its scalable architecture, reducing turnaround time for checks like antenna and PERC ESD. The tool's HyperSync architecture improves performance for full-chip checks, and its Elastic Compute feature optimizes resource utilization. IC Validator is certified by leading foundries and aims to streamline physical verification for advanced designs.

SemiWiki•
SemiEngineering

Blog Review: Apr. 22

Siemens EDA, Synopsys, Cadence, Keysight, Arm, and SEMI experts discuss various tech topics in the latest blog review. Topics include coverage closure challenges in verification, electromagnetic simulation for accurate resistance models, verification complexities of CXL 4.0, ATM security risks, Arm Performance Libraries updates, sensor evolution, and more. Additionally, there are insights on advanced nodes, GaN transistors, DRAM performance, and MLF packaging methods in the Manufacturing, Packaging & Materials newsletter.

SemiEngineering•
The USC Professor Who Pioneered Socially Assistive Robotics

The USC Professor Who Pioneered Socially Assistive Robotics

Maja Matarić, a USC professor, is at the forefront of socially assistive robotics, with her latest creation aiding students' mental health. Bandit, the robot, engages in games with children on the autism spectrum and provides them with positive affirmations. Matarić's work showcases the potential for robots to support individuals in various aspects of their lives, highlighting the intersection of technology and human well-being.

IEEE Spectrum•

We use cookies

We use cookies to ensure you get the best experience on our website. For more information on how we use cookies, please see our cookie policy.