Tech News
Back to home
Technology

Solving the EDA tool fragmentation crisis

Source

SemiWiki

Published

TL;DR

AI Generated

Design teams are facing challenges with EDA tool fragmentation as specialized tools for IC verification struggle to share design data efficiently. The Calibre Connectivity Interface (CCI) aims to bridge this gap by transforming Layout vs. Schematic (LVS) verification data into a universal source that downstream tools can access accurately. CCI operates on the Standard Verification Database (SVDB) to provide rich connectivity data for various analysis tools, including parasitic extraction, electromagnetic simulation, and power integrity analysis. Integration with third-party tools like Empyrean's PEX, Phlexing's GloryEX, Synopsys StarRC, and Cadence QRC showcases CCI's ability to streamline workflows and enhance design accuracy. The article emphasizes the importance of seamless multi-tool integration in modern IC design to improve efficiency and accelerate time-to-market for semiconductor innovation.

Read Full Article

Similar Articles

Two Paths for AI in Semiconductor Manufacturing: Platform Integration vs. Point Solutions

Two Paths for AI in Semiconductor Manufacturing: Platform Integration vs. Point Solutions

Semiconductor manufacturing is increasingly reliant on AI for optimization, with two distinct paths emerging: platform integration and point solutions. Platform integration in North America and Europe emphasizes scalability and long-term value, while China leans towards quick, targeted solutions due to smaller vendors and a need for rapid monetization. These approaches are influenced by market conditions and organizational context, with platform-based models offering structured foundations but requiring upfront investment, while point solutions deliver rapid impact but may lead to fragmentation. A strategic hybrid approach combining both models is being considered for the future of semiconductor AI.

SemiWiki•
How to Overcome the Advanced Node Physical Verification Bottleneck

How to Overcome the Advanced Node Physical Verification Bottleneck

Advanced semiconductor process technology poses challenges in physical verification, the final gate to manufacturing. With shrinking process nodes, the number of checks has quadrupled, leading to bottlenecks in full-chip runs that can take days to weeks. Synopsys IC Validator offers a solution with its scalable architecture, reducing turnaround time for checks like antenna and PERC ESD. The tool's HyperSync architecture improves performance for full-chip checks, and its Elastic Compute feature optimizes resource utilization. IC Validator is certified by leading foundries and aims to streamline physical verification for advanced designs.

SemiWiki•
SemiEngineering

Blog Review: Apr. 22

Siemens EDA, Synopsys, Cadence, Keysight, Arm, and SEMI experts discuss various tech topics in the latest blog review. Topics include coverage closure challenges in verification, electromagnetic simulation for accurate resistance models, verification complexities of CXL 4.0, ATM security risks, Arm Performance Libraries updates, sensor evolution, and more. Additionally, there are insights on advanced nodes, GaN transistors, DRAM performance, and MLF packaging methods in the Manufacturing, Packaging & Materials newsletter.

SemiEngineering•
Why Proof Convergence Matters

Why Proof Convergence Matters

The article discusses the importance of proof convergence in semiconductor verification as chip complexity increases. With more cores, interactions, and reliance on AI for AI chip development, achieving a definitive answer in verification becomes challenging. Ashish Darbari, CEO of Axiomise, emphasizes the impact of functional interactions on safety and security in designs. By identifying common patterns to prevent bugs and improve coverage, time to sign-off can be reduced.

SemiEngineering•

We use cookies

We use cookies to ensure you get the best experience on our website. For more information on how we use cookies, please see our cookie policy.