Smart Handling Of Reset Domain Crossings To Non-Resettable Flip-Flops

The article discusses the challenges of handling reset domain crossings (RDC) in complex system-on-chip (SoC) designs, particularly involving non-resettable registers (NRRs) and asynchronous reset sources. It emphasizes the importance of static RDC verification tools in identifying potential issues like metastability and functional failures. The article proposes a more flexible approach to RDC verification, allowing for path-specific skip-depth configuration and intelligent filtering of safe RDCs to NRRs. By incorporating proactive functional analysis of reset assertion sequences, the proposed methodology aims to reduce false positives and streamline the verification process for designers. The effectiveness of the approach is demonstrated through a reduction in reported unsafe RDCs in multiple SoC designs.