Semiconductor Manufacturing Cybersecurity Consortium (SMCC)—SEMI E187 Compliance Guidance Report

TSMC’s 2nm leak is considered ‘not critical’ — senior gov’t official says company secrets are compartmentalized and unusable in parts

Accelerating The ASIL Journey For Chipmakers

The article discusses the importance of Automotive Safety Integrity Level (ASIL) in ensuring the safety of vehicles as they become more software-defined. ASIL categorizes systems into levels A to D based on potential harm, occurrence frequency, and controllability. Chipmakers need to embed safety features like secure boot and error-correcting code early in the design phase to achieve ASIL compliance. ASIL-certified IP provides advantages like faster development, reduced risk, and increased confidence for chipmakers serving the automotive market. Rambus has achieved ASIL-D certification, enabling them to offer comprehensive safety solutions to customers.

Security Verification In Semiconductor Development

The article discusses the importance of security verification in semiconductor development as advanced chips become more prevalent in daily life. It emphasizes the need for hardware security to protect confidentiality, integrity, and availability in chips. The process involves early vulnerability analysis, data propagation verification, and modeling malicious attacks to ensure chip security. Tools like Synopsys VC SpyGlass and VC Formal are highlighted for detecting vulnerabilities and ensuring data security. The article concludes by stressing the evolving nature of chip security and the role of electronic design automation tools in ensuring secure chip design.

Dr. L.C. Lu on TSMC Advanced Technology Design Solutions

Dr. L.C. Lu, a key figure at TSMC, focuses on design-technology co-optimization, packaging innovations, and AI-driven methodologies for next-gen semiconductor systems. TSMC emphasizes DTCO and DDCL innovations for scaling from N5 to A14 nodes, with NanoFlex and NanoFlex Pro architectures offering efficiency gains. N2P and N2U nodes incorporate advanced DTCO and power delivery optimizations, with hybrid dual-rail architectures achieving significant energy savings. TSMC collaborates with EDA partners for AI integration, enhancing productivity and design quality. Advanced packaging technologies like CoWoS and SoIC play a crucial role in enabling AI scaling, with memory bandwidth and interconnect performance scaling aggressively. TSMC addresses power delivery and thermal management challenges in AI systems through advanced solutions. TSMC's advancements in design methodologies and AI-driven automation promise improved productivity and scalability in chip-package co-design.