Technology
TSMC’s 2nm leak is considered ‘not critical’ — senior gov’t official says company secrets are compartmentalized and unusable in parts
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Tom's Hardware
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Dr. L.C. Lu on TSMC Advanced Technology Design Solutions
Dr. L.C. Lu, a key figure at TSMC, focuses on design-technology co-optimization, packaging innovations, and AI-driven methodologies for next-gen semiconductor systems. TSMC emphasizes DTCO and DDCL innovations for scaling from N5 to A14 nodes, with NanoFlex and NanoFlex Pro architectures offering efficiency gains. N2P and N2U nodes incorporate advanced DTCO and power delivery optimizations, with hybrid dual-rail architectures achieving significant energy savings. TSMC collaborates with EDA partners for AI integration, enhancing productivity and design quality. Advanced packaging technologies like CoWoS and SoIC play a crucial role in enabling AI scaling, with memory bandwidth and interconnect performance scaling aggressively. TSMC addresses power delivery and thermal management challenges in AI systems through advanced solutions. TSMC's advancements in design methodologies and AI-driven automation promise improved productivity and scalability in chip-package co-design.
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Bolt Graphics tapes out its first Zeus GPU test chip on TSMC 12nm — firm touts 17x lower cost of compute
Bolt Graphics has successfully taped out its first Zeus GPU test chip on TSMC's 12nm process, transitioning from FPGA emulation to manufactured silicon. The company claims a significant 17 times lower cost of compute with this move. The test chip will undergo customer benchmarking before a planned production increase in Q4 2027, targeting markets like HPC and graphics rendering. Bolt's Zeus GPU, initially introduced in 2025, aims to offer high performance and efficiency, with plans to utilize more advanced nodes for final production. The company's product pipeline exceeds $500 million, with significant interest from various stakeholders, though specific funding details remain undisclosed.
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TSMC unveils process technology roadmap through 2029 — A12, A13, N2U announced, A16 slips to 2027
TSMC unveiled its process technology roadmap through 2029, introducing A12, A13, and N2U while pushing back A16 to 2027. The company emphasized a segmented strategy for nodes based on end-market requirements rather than a one-size-fits-all approach. A13 and N2U are geared towards client applications, offering incremental improvements and IP reuse, while A16 and A12 target AI and HPC applications with significant performance enhancements. Notably, A13 and A12 will not require High-NA EUV lithography tools, showcasing TSMC's innovative scaling approach.
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Analog Bits Demos Real-Time On-Chip Power Sensing and Delivery on N2P at the TSMC 2026 Technology Symposium
Analog Bits showcased real-time on-chip power sensing and delivery IP on TSMC's N2P process at the TSMC 2026 Technology Symposium. The company addresses power density challenges in AI and HPC systems by leveraging advanced processes and architectural optimizations. The demos include features like LDO for improved power efficiency, droop detector for security, glitch catcher for reliability, and low power PLLs for various applications. These new IPs aim to enhance PPA optimization and on-chip power management for advanced SoCs. CEO Mahesh Tirupattur highlighted the benefits of their integrated on-die LDO and real-time power observability for quick corrective actions.
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