S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development

MachineWare, S2C, and Andes Technology have collaborated to introduce a RISC-V co-emulation solution aimed at streamlining chip development. The solution combines MachineWare’s SIM-V virtual platform, S2C’s Genesis Architect and Prodigy FPGA Prototyping Systems, and Andes’ AX46MPV RISC-V CPU core to facilitate hardware and software co-verification. As RISC-V designs become more intricate, this solution supports a "shift-left" verification strategy, enabling parallel work by hardware and software teams to reduce development time and project risks. MachineWare’s SIM-V platform offers high simulation speed and compatibility with Andes RISC-V cores, while Andes contributes its customizable AX46MPV multicore processor. S2C bridges virtual and physical components through its prototyping systems, allowing for realistic system context and detailed debug visibility. The joint solution aids in pre-silicon software development, hardware/software co-verification, system performance analysis, and custom ISA extension development and debug, ultimately aiming to accelerate time-to-market and enhance software maturity for RISC-V chip design.