Revolutionizing Chip Testing: Navigating Bottlenecks

The article discusses the challenges faced by Design-for-Test (DFT) engineers in testing complex System-on-Chips (SoCs) due to bottlenecks in traditional testing methodologies like IJTAG. It highlights the limitations of serial operations within IJTAG networks, such as time-consuming setup, clocking challenges, and retargeting complexity. Siemens introduced Tessent IJTAG Pro at the International Test Conference 2025 as a solution to address these challenges by transforming serial IJTAG operations into high-speed parallel processes. This new tool leverages the Tessent Streaming Scan Network (SSN) bus to improve efficiency, access custom hardware, and simplify retargeting, ultimately enhancing chip testing capabilities.