Technology

Revolutionizing Chip Testing: Navigating Bottlenecks

Source

SemiEngineering

Published

Oct 14, 2025

TL;DR

AI Generated

The article discusses the challenges faced by Design-for-Test (DFT) engineers in testing complex System-on-Chips (SoCs) due to bottlenecks in traditional testing methodologies like IJTAG. It highlights the limitations of serial operations within IJTAG networks, such as time-consuming setup, clocking challenges, and retargeting complexity. Siemens introduced Tessent IJTAG Pro at the International Test Conference 2025 as a solution to address these challenges by transforming serial IJTAG operations into high-speed parallel processes. This new tool leverages the Tessent Streaming Scan Network (SSN) bus to improve efficiency, access custom hardware, and simplify retargeting, ultimately enhancing chip testing capabilities.

Read Full Article

The USC Professor Who Pioneered Socially Assistive Robotics

Maja Matarić, a USC professor, is at the forefront of socially assistive robotics, with her latest creation aiding students' mental health. Bandit, the robot, engages in games with children on the autism spectrum and provides them with positive affirmations. Matarić's work showcases the potential for robots to support individuals in various aspects of their lives, highlighting the intersection of technology and human well-being.

IEEE Spectrum•

1 week ago

Emulation-based SoC Security Verification (U. of Florida)

Researchers at the University of Florida have published a technical paper titled "Emulation-based System-on-Chip Security Verification: Challenges and Opportunities," focusing on the importance of security validation in semiconductor design due to increasing system-on-chip (SoC) complexity. The paper highlights hardware emulation as a crucial pre-silicon verification technology that allows for high-throughput execution of designs under realistic conditions for security analysis. It covers various aspects of emulation-based security verification workflows, including instrumentation, stimulus generation, and runtime monitoring. The paper also discusses emerging trends like AI-assisted emulation and automated vulnerability assessment, positioning emulation as a key element in ensuring hardware security.

SemiEngineering•

2 weeks ago

NoC Matters: Designing the Backbone of Next-Gen AI SoCs

The role of the network-on-chip (NoC) in modern AI SoC design has become crucial for system performance, power efficiency, and scalability, with data movement being a key factor. NoC architecture must be a primary design consideration due to the increasing complexity of AI-centric SoCs with diverse accelerators. Coherency models, specialized NoC hardware units, and physical floorplanning are essential aspects that impact system performance and efficiency. A structured methodology for NoC development, including traffic modeling, topology exploration, and physical partitioning, is crucial for successful implementation. Treating the NoC as a fundamental system-level design element is essential for achieving scalable performance and efficient power usage in complex AI SoCs.

SemiWiki•

2 weeks ago

Intel developing two-lever retention mechanism for LGA 1954 socket, according to new leak — Premium Nova Lake-S motherboards will feature 2L-ILM sockets

Intel is reportedly working on a new two-lever retention mechanism for the LGA 1954 socket, set to be featured in the Premium Nova Lake-S motherboards. This mechanism, named "2L-ILM," aims to enhance cooling performance by ensuring better thermal contact between the CPU's integrated heat spreader (IHS) and the heatsink. The design with two levers covering the entire perimeter of the socket is intended to prevent hotspots and potential CPU bending due to uneven contact pressure. This development signifies Intel's focus on refining even minor details for its upcoming Nova Lake-S CPU lineup, emphasizing the importance of thermal management in high-performance computing.

Tom's Hardware•

3 weeks ago