Technology

Reconfigurable Single-Walled CNT FeFET (Univ. of Pennsylvania, Yonsei et al.)

Source

SemiEngineering

Published

Aug 25, 2025

TL;DR

AI Generated

Researchers from the University of Pennsylvania, Yonsei University, and others have published a paper on "Reconfigurable single-walled carbon nanotube ferroelectric field-effect transistors." The study focuses on creating scalable reconfigurable devices that integrate carbon nanotubes with a ferroelectric gate dielectric, showcasing high on-state currents, on/off ratios exceeding 105, and excellent memory characteristics. The devices can switch between p- and n-channel transistors, enabling the realization of ternary content-addressable memory with fewer components than traditional silicon-based circuits. This advancement could lead to more compact and power-efficient integrated circuits.

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A Comparative Study With Horizontal and Verticals FETs (POSTECH, Georgia Tech)

Researchers from POSTECH and Georgia Tech published a technical paper comparing vertical FET (VFET) structures with horizontal FETs (HFET) for Angstrom nodes. The study introduces two novel VFET designs and evaluates their competitiveness against nanosheet FET (NSFET) and forksheet FET (FSFET). The findings show that the fork-shaped channel VFET (VFETFS) outperforms conventional VFET (VFETCON) and FSFET in terms of footprint size and performance due to reduced capacitance. Strategies like expanding the silicide area improve drive current and enable VFETFS to surpass FSFET for NFET. The study also explores a secondary device architecture, VFETFS with back-side contact (VFETBSC), which further reduces footprint and enhances performance for both N/PFET.

SemiEngineering•

9 months ago

Ferroelectric Helps Break Transistor Limits

IEEE Spectrum•

10 months ago

Dr. L.C. Lu on TSMC Advanced Technology Design Solutions

Dr. L.C. Lu, a key figure at TSMC, focuses on design-technology co-optimization, packaging innovations, and AI-driven methodologies for next-gen semiconductor systems. TSMC emphasizes DTCO and DDCL innovations for scaling from N5 to A14 nodes, with NanoFlex and NanoFlex Pro architectures offering efficiency gains. N2P and N2U nodes incorporate advanced DTCO and power delivery optimizations, with hybrid dual-rail architectures achieving significant energy savings. TSMC collaborates with EDA partners for AI integration, enhancing productivity and design quality. Advanced packaging technologies like CoWoS and SoIC play a crucial role in enabling AI scaling, with memory bandwidth and interconnect performance scaling aggressively. TSMC addresses power delivery and thermal management challenges in AI systems through advanced solutions. TSMC's advancements in design methodologies and AI-driven automation promise improved productivity and scalability in chip-package co-design.

SemiWiki•

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MindsEye's sabotage mission is being slammed as dull and pointless

Build A Rocket Boy accuses individuals of sabotaging MindsEye's launch, spending over €1 million on damaging efforts. The studio integrates the controversy into a new in-game mission, Blacklist, to showcase evidence of sabotage to players. However, reports describe the mission as lackluster and failing to deliver a compelling narrative. Critics attribute the launch issues to internal problems, such as management and design decisions, casting doubt on the sabotage claims. The saga continues as MindsEye's post-launch turmoil unfolds.

TweakTown•