Ferroelectric Helps Break Transistor Limits
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AMD's CEO Dr. Lisa Su is set to deliver the opening keynote at CES 2026. The article contains technical code and scripts related to the website's functionality. Dr. Lisa Su's keynote is expected to cover AMD's latest innovations and advancements in the tech industry. The event will likely showcase new products and technologies from AMD.
Researchers from POSTECH and Georgia Tech published a technical paper comparing vertical FET (VFET) structures with horizontal FETs (HFET) for Angstrom nodes. The study introduces two novel VFET designs and evaluates their competitiveness against nanosheet FET (NSFET) and forksheet FET (FSFET). The findings show that the fork-shaped channel VFET (VFETFS) outperforms conventional VFET (VFETCON) and FSFET in terms of footprint size and performance due to reduced capacitance. Strategies like expanding the silicide area improve drive current and enable VFETFS to surpass FSFET for NFET. The study also explores a secondary device architecture, VFETFS with back-side contact (VFETBSC), which further reduces footprint and enhances performance for both N/PFET.
Researchers from the University of Pennsylvania, Yonsei University, and others have published a paper on "Reconfigurable single-walled carbon nanotube ferroelectric field-effect transistors." The study focuses on creating scalable reconfigurable devices that integrate carbon nanotubes with a ferroelectric gate dielectric, showcasing high on-state currents, on/off ratios exceeding 105, and excellent memory characteristics. The devices can switch between p- and n-channel transistors, enabling the realization of ternary content-addressable memory with fewer components than traditional silicon-based circuits. This advancement could lead to more compact and power-efficient integrated circuits.
Dr. L.C. Lu, a key figure at TSMC, focuses on design-technology co-optimization, packaging innovations, and AI-driven methodologies for next-gen semiconductor systems. TSMC emphasizes DTCO and DDCL innovations for scaling from N5 to A14 nodes, with NanoFlex and NanoFlex Pro architectures offering efficiency gains. N2P and N2U nodes incorporate advanced DTCO and power delivery optimizations, with hybrid dual-rail architectures achieving significant energy savings. TSMC collaborates with EDA partners for AI integration, enhancing productivity and design quality. Advanced packaging technologies like CoWoS and SoIC play a crucial role in enabling AI scaling, with memory bandwidth and interconnect performance scaling aggressively. TSMC addresses power delivery and thermal management challenges in AI systems through advanced solutions. TSMC's advancements in design methodologies and AI-driven automation promise improved productivity and scalability in chip-package co-design.
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