Technology

Meeting High-Frequency And Power Density Challenges With Flip Chip MLF Packaging

Source

SemiEngineering

Published

Apr 16, 2026

TL;DR

AI Generated

The article discusses how flip chip MicroLeadFrame (fcMLF) packaging addresses challenges related to high-frequency and power density in semiconductor devices. It highlights the evolution of semiconductor scaling and the need for improved electrical performance and thermal dissipation in modern compact form factors. The article explains how fcMLF technology offers optimized signal paths, reduced parasitics, and enhanced thermal performance compared to traditional wirebond MLF solutions. It also emphasizes the importance of mitigating electromagnetic interference (EMI) and optimizing package inductance for improved signal integrity. Additionally, the article explores the manufacturing efficiency and cost-effectiveness of fcMLF packages, making them suitable for various applications such as power management ICs and RF devices.

Read Full Article

Read-Centric DTCO for IGZO FeFETs 3D Heterogeneous AI memories (imec, KU Leuven)

Researchers from imec and KU Leuven have published a technical paper titled "DTCO of NOR-Type IGZO FeFETs for 3D Heterogeneous AI Memories: A Read-Centric Perspective." The paper evaluates the feasibility of using NOR-type IGZO FeFETs for 3D heterogeneous AI memories from a read-centric design-technology co-optimization (DTCO) standpoint. The study covers various memory architectures, including on-chip back-end-of-line (BEOL) RAMs, hybrid-bonded memory chiplets, and off-chip monolithically integrated 3D FeNOR storage-class memories (SCMs). The research aims to advance the development of efficient and effective memory designs for AI applications.

SemiEngineering•

1 week ago

SemiEngineering

Reduce Memory Redesigns With Shift-Left

The article discusses the importance of shifting contention analysis left to the schematic stage in memory design to prevent late-stage rework. It highlights how complex memory architectures can lead to catastrophic system failures if contention issues are not addressed early. By analyzing transistor-level connectivity and power domain crossings at the schematic stage, teams can detect and resolve risks before they impact silicon, leading to predictable convergence on first-time-right silicon. This shift-left methodology improves design efficiency, reduces costs, enhances predictability, and compresses development schedules. Engineering managers are advised to integrate schematic-level contention checking into design reviews and milestone gates to reap these organizational benefits.

SemiEngineering•

1 week ago

SemiEngineering

Orbital Data Centers Are Souped-Up Satellites – For Now

Orbital data centers, currently referred to as compute centers in space, are being developed to handle AI workloads for people on Earth. These centers are powered by sun-synchronous solar energy but face challenges due to Earth's magnetic field weakening at the poles, leading to radiation effects on advanced node architectures. Companies like SpaceX and Blue Origin are investing in building satellite constellations with increased compute capabilities to meet the growing demand for AI processing power. However, technical challenges such as power generation, thermal management, and space debris need to be addressed before these orbital data centers become mainstream.

SemiEngineering•

1 week ago

Scaling Nanoribbon Transistors with Monolayer TMDs (Stanford, Chalmers, Horiba, SLAC)

Researchers from Stanford University, Chalmers University of Technology, HORIBA Scientific, and SLAC National Accelerator Laboratory have developed nanoribbon transistors using monolayer transition metal dichalcogenides (TMDs). These transistors feature n- and p-type operation with channel lengths and widths as small as 25-30 nm. The fabrication process includes anchored contacts to prevent nanoribbon delamination, and when integrated with thin high-k gate dielectrics, the devices exhibit impressive on-state currents for various TMD materials. This advancement positions top-down patterned 2DS nanoribbons as promising components for future nanosheet transistor architectures.

SemiEngineering•

1 week ago

Read-Centric DTCO for IGZO FeFETs 3D Heterogeneous AI memories (imec, KU Leuven)

SemiEngineering•

1 week ago

SemiEngineering

Reduce Memory Redesigns With Shift-Left

SemiEngineering•

1 week ago

SemiEngineering

Orbital Data Centers Are Souped-Up Satellites – For Now

SemiEngineering•

1 week ago

Scaling Nanoribbon Transistors with Monolayer TMDs (Stanford, Chalmers, Horiba, SLAC)

SemiEngineering•

1 week ago

Meeting High-Frequency And Power Density Challenges With Flip Chip MLF Packaging

TL;DR

Similar Articles

Read-Centric DTCO for IGZO FeFETs 3D Heterogeneous AI memories (imec, KU Leuven)

Reduce Memory Redesigns With Shift-Left

Orbital Data Centers Are Souped-Up Satellites – For Now

Scaling Nanoribbon Transistors with Monolayer TMDs (Stanford, Chalmers, Horiba, SLAC)

We use cookies

Meeting High-Frequency And Power Density Challenges With Flip Chip MLF Packaging

TL;DR

Similar Articles

Read-Centric DTCO for IGZO FeFETs 3D Heterogeneous AI memories (imec, KU Leuven)

Reduce Memory Redesigns With Shift-Left

Orbital Data Centers Are Souped-Up Satellites – For Now

Scaling Nanoribbon Transistors with Monolayer TMDs (Stanford, Chalmers, Horiba, SLAC)