How TSMC managed to increase efficiency of ASML's EUV tools: System-level optimizations and in-house pellicles —chipmaker boosted EUV-driven wafer production by 30x over six years while reducing power consumption by 24%

TSMC has significantly increased the efficiency of ASML's EUV lithography tools by implementing system-level optimizations and developing in-house pellicles. Over six years, TSMC boosted EUV-driven wafer production by 30 times while reducing power consumption by 24%. By refining exposure doses, upgrading photoresist materials, and enhancing scanner utilization efficiency, TSMC doubled wafer output per EUV tool per day since 2019. The company also made substantial advancements in pellicle technology, achieving longer lifespan, increased wafer output, and reduced defects. TSMC's efforts demonstrate its commitment to controlling the full EUV stack and improving energy efficiency in chip manufacturing.