Technology

Chip Industry Technical Paper Roundup: May 5

Source

SemiEngineering

Published

May 5, 2026

TL;DR

AI Generated

The article discusses various technical papers in the chip industry, including topics like 3D-stacked near-memory decoding, ESD protection for chiplets, thermal management in advanced packaging, quantum circuits on chiplets, AI for formal verification, nanostructure characterization, liquid cooling for advanced packages, and photonic coupler arrays. These papers come from research organizations like the University of Edinburgh, Peking University, UC Riverside, Georgia Tech, TU Munich, Infineon, Aalto University, KAIST, and the University of Oxford. The papers cover a range of cutting-edge technologies and advancements in the semiconductor industry.

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What’s Really Needed For Advanced Test?

The article discusses the importance of data quality in advanced testing within the semiconductor industry. It highlights the challenges related to data plumbing and the need for clean, complete, and correctly associated data. The article emphasizes the significance of good data infrastructure, particularly in metadata consistency and direct data collection at the point of measurement. It also touches on the application of machine learning in test operations, pointing out the current limitations in real-time model inference. Overall, the article underscores the critical role of data quality in enabling intelligent testing and the need for investments in data infrastructure.

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8 hours ago

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Research Bits: May 11

Researchers have developed a non-destructive terahertz inspection technique that allows observation of electrical activity inside semiconductor devices while they are operational, using ultra-sensitive detection systems. Another study introduced a piezoelectric step-down converter that achieved peak efficiency of 96.2% by combining a resonator with small capacitors, potentially offering smaller, more energy-dense, and efficient converters for data centers. Additionally, a silicon oscillatory Ising machine was created by researchers at KAIST, enabling the solution of combinatorial optimization problems using conventional silicon CMOS processes, with potential applications in various industrial fields.

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1 day ago

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The Emergence Of Electronics Digital Twins For Software-Defined Vehicles

The article discusses the emergence of electronics digital twins (eDTs) for software-defined vehicles (SDVs). Traditional digital twins have been used to model mechanical systems, but with the increasing reliance on electronics and software in vehicles, eDTs are now designed to model the complete electronics and software systems of modern vehicles. These eDTs go beyond development and support the full vehicle lifecycle, enabling continuous software updates and new revenue models based on software-driven features. The article also highlights the importance of eDT platforms, diverse use cases across industries, and the need for clear business objectives when implementing eDTs.

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High-NA EU Lithography: Extending The STCC Formula (Science Tokyo)

Researchers at the Institute of Science Tokyo have published a technical paper on high-NA EU lithography, focusing on the impact of polarization in extreme ultraviolet lithography. The paper aims to extend the STCC formula to include polarization effects for more accurate simulations in high-NA EUV lithography. This work was presented at SPIE Advanced Lithography + Patterning 2026 and is available in the Journal of Micro/Nanopatterning, Materials, and Metrology. The authors include Hiroyoshi Tanabe, Moe Sugiyama, Masayuki Shimoda, and Atsushi Takahashi.

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Research Bits: May 11

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Chip Industry Technical Paper Roundup: May 5

TL;DR

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Chip Industry Technical Paper Roundup: May 5

TL;DR

Similar Articles

What’s Really Needed For Advanced Test?

Research Bits: May 11

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High-NA EU Lithography: Extending The STCC Formula (Science Tokyo)