Accelerating SRAM Design Cycles: MediaTek’s Adoption of Siemens EDA’s Additive AI Technology at TSMC OIP 2025

Siemens EDA and MediaTek showcased the benefits of Additive Learning technology in accelerating SRAM design cycles at TSMC OIP 2025. SRAM's significant role in mobile SoC development, occupying 40% of chip area, influences yield and performance. By integrating Additive Learning into Siemens EDA's Solido tools, MediaTek achieved speedups of 20-67x in verification processes compared to traditional methods. This AI-driven methodology reduces the number of simulations needed for verification while maintaining SPICE-level accuracy, showcasing the potential of AI in semiconductor workflows for greater efficiencies in future nodes. The collaboration between Siemens EDA and MediaTek sets a benchmark for AI integration in chip design, promising faster time-to-market for high-yield SoCs.