3D DRAM with CBA Technology (Georgia Tech)

Researchers at Georgia Tech have published a technical paper on "System-Technology Co-Optimization of Bitline Routing and Bonding Pathways in Monolithic 3D DRAM Architectures." The paper discusses the challenges in 3D DRAM density scaling and introduces a CMOS-Bonded-Array (CBA) with amorphous oxide semiconductor selectors to manage routing congestion and parasitics. The optimized design achieves a bit density of 2.6 Gb/mm^2, representing significant density scaling over traditional 2D DRAM. Additionally, the design shows improvements in row cycle time and a reduction in read/write energy.