SemiEngineering
Chip Industry Technical Paper Roundup: Nov. 4
The article discusses various technical papers in the chip industry, including topics like MIT's AI accelerators, SOT-based MRAM design at 7nm, in-DRAM TRNG using multiple-row activation, chiplet-locality for memory mapping, FeRAM vs. DRAM performance, automotive SoC vulnerabilities, EUV + DSA progress, and a multimodal chip physical design engineer assistant. The papers cover a range of research areas from different institutions like MIT Lincoln Laboratory, Georgia Tech, Intel, ETH Zurich, and more. These papers provide insights into cutting-edge developments and challenges in the semiconductor industry.
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