Challenges In Scaling Chips To 2nm And Below
Chips scaling to 2nm and below face challenges in terms of power improvements per watt, increased complexity, and higher costs. Solutions to these challenges often create new problems due to less margin for tradeoffs, necessitating larger interposers, more chiplets, and complex packages. Precision is crucial throughout the design-to-manufacturing flow, requiring shifts to technologies that have been underutilized. Companies are customizing designs for specific data types and operating conditions, leading to vendor- or workload-specific designs at the leading edge. The transition to 2nm logic involves extraordinary complexity in transistor design, materials, and performance metrics, with costs exceeding $100 million from design to working silicon.