Articles tagged with "Semiconductor, ClockAnalysis, MarginOptimization"

Webinar – How to Reclaim Margin in Advanced Nodes

The webinar "How to Reclaim Margin in Advanced Nodes" addresses the issue of excessive guard banding in sub-5nm designs, resulting in reduced performance and profit. Presenter Dave Johnson discusses the impact of modeling uncertainty and the "abstraction tax" on design margins, emphasizing the need to reclaim wasted margin at advanced nodes. He explains the challenges faced at 3nm due to the pessimism wall and offers insights into ClockEdge's solution, the Veridian Engine, which enables full clock SPICE-level analysis for over 100 million gate designs. The webinar highlights the importance of optimizing clock power and overcoming clock network challenges to unlock superior performance and profitability in advanced node design.