Articles tagged with "SOT-MRAM, Last-Level Caches, Heterogeneous System Scaling, Design-Technology Co-Optimization, MRAM Technology"

Cross-Node Scaling Potential of SOT-MRAM for Last-Level Caches (imec)

Researchers at imec, Leuven, and 3001 Belgium have published a technical paper on the potential of SOT-MRAM for last-level caches (LLCs) in heterogeneous system scaling. The study explores Design-Technology Co-Optimization (DTCO) to evaluate bitcell footprint at 7nm technology, focusing on read and write power-performance implications. They propose using BEOL read selectors (BEOL RSs) to reduce bitcell area by 10-40%, matching sub-N3 SRAM. While BEOL RS-based bitcells can meet SOT switching current requirements, there are tradeoffs in read latency and energy costs compared to conventional SOT-MRAMs. The study highlights the challenges and prospects of BEOL RSs for power-performance-area scaling of SOT-MRAM.