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Articles tagged with "RTL, Hardware, Synthesis"

Balancing Leakage Reduction with Correctness Preservation in RTL Code Generation (Univ. of Central Florida)

Balancing Leakage Reduction with Correctness Preservation in RTL Code Generation (Univ. of Central Florida)

Researchers at the University of Central Florida have published a technical paper titled "CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage." The paper addresses the risks posed by Large Language Models (LLMs) in RTL hardware synthesis, where training data memorization can unintentionally expose proprietary designs. The proposed defense strategy, CircuitGuard, introduces a novel RTL-aware similarity metric and an activation-level steering method to balance leakage reduction with correctness preservation. Empirical evaluation shows that CircuitGuard can reduce semantic similarity to proprietary patterns by up to 80% while maintaining generation quality and enabling robust memorization mitigation across circuit categories without retraining.

SemiEngineering

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