Samsung touts 96% lower-power NAND design — researchers investigate design based on ferroelectric transistors
Samsung researchers have developed a low-power NAND design using ferroelectric transistors, aiming for a 96% reduction in power consumption. The design features a ferroelectric field-effect transistor (FeFET) for future 3D NAND, with a near-zero pass-voltage operation. This design could significantly reduce power consumption in NAND arrays with multiple layers. While Samsung has not announced any product plans based on this research yet, the study lays the groundwork for potential low-power NAND generations beyond current technologies.
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