Articles tagged with "HBM Stacking, High-Bandwidth Memory, Semiconductor Engineering, Hybrid Bonding, Microbump Alignment"

Challenges In Stacking HBM

AI data centers are aiming for denser high-bandwidth memory, with stacking layers expected to increase from 8 to 24 by 2030. The main challenge lies in the interconnects and aligning microbumps, particularly as bump pitch decreases to less than 10 microns at 16 layers. Damon Tsai from Onto Innovation discusses strategies to reduce stress-induced warpage, necessary changes in HBM architectures, and the implications of incorporating hybrid bonding and co-packaged optics in these devices. The article highlights the complexities and advancements needed in stacking HBM to meet future demands in semiconductor engineering.