Ambitious hacker reduces worst-case memory latency by up to 93%, but with severe downsides — 1960s bottleneck overcome by hedging memory accesses to avoid running into DRAM refresh stalls
A hacker named LaurieWired developed a method called TailSlayer to reduce memory latency by up to 93% by avoiding DRAM refresh stalls. By duplicating the working set across memory addressing boundaries and running operations simultaneously on different CPU cores, she achieved significant latency reductions on consumer and server hardware. Her technique is particularly beneficial for sensitive workloads like high-frequency trading, where deterministic memory latency is crucial. However, the method requires duplicating the working set for each memory channel, leading to increased memory requirements that may limit its applicability to certain use cases. LaurieWired's detailed video and GitHub repository provide further insights into her innovative approach.