Two Open RISC-V Projects Chart Divergent Paths to High Performance

Two significant RISC-V projects, Ara and XiangShan, showcase different approaches to scaling performance. Ara focuses on explicit vector processing without speculation, prioritizing efficiency for parallel workloads. Its memory system lacks private L1 caches and emphasizes software-managed memory. XiangShan, on the other hand, follows a traditional high-performance CPU path with deep pipelines and speculation. While Ara serves as a reference platform, XiangShan has progressed to multiple tape-outs and commercialization without traditional IP licensing. Both projects demonstrate the diversity of architectural exploration within the RISC-V ecosystem.