Back to home
Technology

TSMC increases Arizona internships to feed its Phoenix fabs — CHIPS-fueled supply chain begins to take shape

Source

Tom's Hardware

Published

TL;DR

AI Generated

TSMC has significantly expanded its Arizona internship program, bringing in over 200 students from around 60 colleges to staff its advanced-node fabs near Phoenix. The company has begun producing 4nm chips at its first Phoenix fab and received $6.6 billion in CHIPS Act subsidies for a third fab supporting upcoming 2nm processes. TSMC is also utilizing a new $2 billion packaging facility in Peoria to handle essential technologies for high-performance chips, keeping more of the supply chain in the U.S. Local partnerships and workforce training programs are crucial for sustaining the talent needed for a long-term domestic supply chain.

Read Full Article

Similar Articles

Dr. L.C. Lu on TSMC Advanced Technology Design Solutions

Dr. L.C. Lu on TSMC Advanced Technology Design Solutions

Dr. L.C. Lu, a key figure at TSMC, focuses on design-technology co-optimization, packaging innovations, and AI-driven methodologies for next-gen semiconductor systems. TSMC emphasizes DTCO and DDCL innovations for scaling from N5 to A14 nodes, with NanoFlex and NanoFlex Pro architectures offering efficiency gains. N2P and N2U nodes incorporate advanced DTCO and power delivery optimizations, with hybrid dual-rail architectures achieving significant energy savings. TSMC collaborates with EDA partners for AI integration, enhancing productivity and design quality. Advanced packaging technologies like CoWoS and SoIC play a crucial role in enabling AI scaling, with memory bandwidth and interconnect performance scaling aggressively. TSMC addresses power delivery and thermal management challenges in AI systems through advanced solutions. TSMC's advancements in design methodologies and AI-driven automation promise improved productivity and scalability in chip-package co-design.

SemiWiki
More details emerge about how Intel now earns more revenue from each wafer by looking to the edges — analyst reports say reduced yield variability across each wafer leads to more sellable CPUs

More details emerge about how Intel now earns more revenue from each wafer by looking to the edges — analyst reports say reduced yield variability across each wafer leads to more sellable CPUs

Intel has seen improved revenue per wafer by reducing yield variability across each wafer, resulting in more sellable CPUs. The company's focus on tightening yield distribution across the wafer edges has led to increased margins and productivity. By implementing edge-specific process correction methods, Intel can extract more high-quality and sellable dies from a single wafer. These improvements are node-independent and have been attributed to disciplined execution improvements under new manufacturing leadership. Intel's efforts have led to better output and demand for CPUs, with even lower-quality chips now being sold as viable products.

Tom's Hardware
Bolt Graphics tapes out its first Zeus GPU test chip on TSMC 12nm — firm touts 17x lower cost of compute

Bolt Graphics tapes out its first Zeus GPU test chip on TSMC 12nm — firm touts 17x lower cost of compute

Bolt Graphics has successfully taped out its first Zeus GPU test chip on TSMC's 12nm process, transitioning from FPGA emulation to manufactured silicon. The company claims a significant 17 times lower cost of compute with this move. The test chip will undergo customer benchmarking before a planned production increase in Q4 2027, targeting markets like HPC and graphics rendering. Bolt's Zeus GPU, initially introduced in 2025, aims to offer high performance and efficiency, with plans to utilize more advanced nodes for final production. The company's product pipeline exceeds $500 million, with significant interest from various stakeholders, though specific funding details remain undisclosed.

Tom's Hardware
TSMC unveils process technology roadmap through 2029 — A12, A13, N2U announced, A16 slips to 2027

TSMC unveils process technology roadmap through 2029 — A12, A13, N2U announced, A16 slips to 2027

TSMC unveiled its process technology roadmap through 2029, introducing A12, A13, and N2U while pushing back A16 to 2027. The company emphasized a segmented strategy for nodes based on end-market requirements rather than a one-size-fits-all approach. A13 and N2U are geared towards client applications, offering incremental improvements and IP reuse, while A16 and A12 target AI and HPC applications with significant performance enhancements. Notably, A13 and A12 will not require High-NA EUV lithography tools, showcasing TSMC's innovative scaling approach.

Tom's Hardware

We use cookies

We use cookies to ensure you get the best experience on our website. For more information on how we use cookies, please see our cookie policy.