Modeling Chiplet Latency with VisualSim Architect

The article discusses how VisualSim Architect from Mirabilis Design enables engineers to model complex multi-die and chiplet-based systems before implementation, highlighting the importance of UCIe latency analysis when integrating chiplets from different vendors. It explores the comparison between 2- and 4-die CPU configurations to reveal performance, power, and thermal tradeoffs. Deepak Shankar, the Founder of Mirabilis Design, demonstrates the impact of transmitting different byte sizes across systems and the latency differences between 2-die and 4-die CPU models. The simulation results emphasize the significance of early optimization through system modeling using VisualSim Architect.