Leaker claims AMD Zen 6 will feature 48MB of L3 cache — keeping L3 cache-to-core ratio the same as Zen 5 with Zen 6's 12-core CCD

A leaker has revealed that AMD's upcoming Zen 6 CPU architecture will include a larger L3 cache of 48MB to accommodate the new 12-core CCD design, maintaining the L3 cache-to-core ratio seen in Zen 5. The Zen 6 architecture is expected to have a larger die size of 76mm² compared to Zen 5's 71mm², marking the first time an AMD architecture will have a larger footprint than its predecessor since Zen 3. The introduction of a 12-core CCD in Zen 6 will enable cores to share data across a unified L3 cache, enhancing multi-threaded performance. AMD plans to use TSMC's N2 process for Zen 6, offering increased transistor density and performance.