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HW/SW Co-Design to Retarget the Compiler For RISC-V Custom Instructions (Tampere Univ.)

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SemiEngineering

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Researchers at Tampere University have published a technical paper on "Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions." The paper discusses the benefits of custom instruction set extensions for performance and energy efficiency in specific applications. By leveraging hardware/software co-design, designers can create hardware implementations and retarget the compiler using high-level instruction set descriptions. The challenge lies in coupling hardware extensions with the processor core, but the researchers introduce a HW/SW co-design toolset to address this. The toolset can adapt to user-defined architecture descriptions, retarget the compiler, and generate co-processors interfacing with standard RISC-V processor interfaces. Integration of co-processors with CVA6 and Rocket core showed significant execution time reductions with minimal area overhead.

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