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Carrier Mapping in Sub-2nm Node NSFETs with SSRM (imec, KU Leuven)

Source

SemiEngineering

Published

TL;DR

AI Generated

Researchers from imec and KU Leuven have published a technical paper on "Carrier Mapping in Sub-2nm Node Nanosheet Transistors with Scanning Spreading Resistance Microscopy." The paper discusses the importance of controlling parasitic resistance in gate-all-around architectures like Nanosheet-FETs for the 2nm node and beyond. They have made advancements in scanning spreading resistance microscopy (SSRM) to enable carrier mapping within 5.5 nm thick nanosheet channels. The study demonstrates how SSRM can provide valuable feedback on junction formation in advanced gate-all-around devices by mapping carrier profiles accurately.