Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers

The article discusses the implementation of backside power delivery networks (BPDN) in semiconductor chips, which involves delivering power directly to transistors from below the wafer. This architectural change aims to enhance processor performance, reduce power losses, and improve power efficiency. Leading IC manufacturers like Intel, Samsung, and TSMC are making progress in implementing BPDN, especially with the transition to nanosheet FETs. Backside power delivery networks offer benefits such as reducing voltage drop by up to 30%, improving power integrity, and enabling a looser metal pitch on the frontside interconnects. However, challenges include aligning backside interconnects with frontside vias and addressing thermal issues associated with hot chips.