Automated Security Assertion Generation Using LLMs (U. of Florida)

A technical paper titled "Assertain: Automated Security Assertion Generation Using Large Language Models" by the University of Florida introduces Assertain, an automated framework that generates security properties and SystemVerilog Assertions for hardware designs. By leveraging large language models and self-reflection refinement, Assertain improves assertion quality and reduces manual effort in hardware security verification. In evaluations on 11 hardware designs, Assertain outperformed GPT-5 in correct assertion generation, unique CWE coverage, and architectural flaw detection. The framework significantly enhances vulnerability coverage in hardware security verification.