AMD's upcoming RDNA 5 GPUs might improve dual-issue execution & use shader units more efficiently — LLVM patch adds new FMA instruction to ease compiling

AMD's upcoming RDNA 5 GPUs are set to enhance dual-issue execution and optimize shader unit usage, potentially boosting FP32 throughput significantly. A new LLVM patch introduces a new FMA instruction to facilitate compiling for improved performance. The addition of a new instruction format, VOPD3, is designed to enhance dual-issue VALU efficiency by supporting 3-operand instructions like fused multiply-add. These enhancements aim to reduce wait times for shader units, making each instruction more efficient, particularly beneficial for demanding tasks like rendering. While RDNA 5 is still in development, these architectural improvements could lead to more consistent and easier achievement of advertised FP32 throughput.