Advances in ATPG from Synopsys

Synopsys has enhanced its ATPG technology to be timing-aware, power-aware, and utilize AI to reduce test costs. The timing-aware ATPG includes fault models that consider transition delays, slack-based path delays, and hold times, with new features addressing challenges like SDC integration. Power-aware ATPG features aim to generate power-friendly patterns and manage power during test operations. The integration of AI technology called TSO.ai with TestMAX ATPG helps optimize test cycles without changing the tool flow. These advancements aim to improve fault coverage, power efficiency, and test cycle optimization for chip testing.