Technology

Advances in ATPG from Synopsys

Source

SemiWiki

Published

Feb 2, 2026

TL;DR

AI Generated

Synopsys has enhanced its ATPG technology to be timing-aware, power-aware, and utilize AI to reduce test costs. The timing-aware ATPG includes fault models that consider transition delays, slack-based path delays, and hold times, with new features addressing challenges like SDC integration. Power-aware ATPG features aim to generate power-friendly patterns and manage power during test operations. The integration of AI technology called TSO.ai with TestMAX ATPG helps optimize test cycles without changing the tool flow. These advancements aim to improve fault coverage, power efficiency, and test cycle optimization for chip testing.

Read Full Article

CISCO ASIC Success with Synopsys SLM IPs

Cisco has been facing challenges in ensuring reliability, performance, and power efficiency in its high-performance networking silicon due to increasing transistor densities. To address this, Cisco has adopted Synopsys Silicon Lifecycle Management (SLM) IPs in its latest Silicon One ASICs, incorporating embedded monitors and analytics capabilities for real-time observability. The deployment of Synopsys SLM IPs, including the Process, Voltage, and Temperature Monitor subsystem, has enabled Cisco to optimize power and performance dynamically based on immediate conditions. By leveraging these IPs, Cisco has achieved enhanced observability, proactive reliability management, and improved lifecycle optimization for its ASIC designs, setting a new benchmark in the networking domain.

SemiWiki•

5 months ago

Dr. L.C. Lu on TSMC Advanced Technology Design Solutions

Dr. L.C. Lu, a key figure at TSMC, focuses on design-technology co-optimization, packaging innovations, and AI-driven methodologies for next-gen semiconductor systems. TSMC emphasizes DTCO and DDCL innovations for scaling from N5 to A14 nodes, with NanoFlex and NanoFlex Pro architectures offering efficiency gains. N2P and N2U nodes incorporate advanced DTCO and power delivery optimizations, with hybrid dual-rail architectures achieving significant energy savings. TSMC collaborates with EDA partners for AI integration, enhancing productivity and design quality. Advanced packaging technologies like CoWoS and SoIC play a crucial role in enabling AI scaling, with memory bandwidth and interconnect performance scaling aggressively. TSMC addresses power delivery and thermal management challenges in AI systems through advanced solutions. TSMC's advancements in design methodologies and AI-driven automation promise improved productivity and scalability in chip-package co-design.

SemiWiki•

3 hours ago

MindsEye's sabotage mission is being slammed as dull and pointless

Build A Rocket Boy accuses individuals of sabotaging MindsEye's launch, spending over €1 million on damaging efforts. The studio integrates the controversy into a new in-game mission, Blacklist, to showcase evidence of sabotage to players. However, reports describe the mission as lackluster and failing to deliver a compelling narrative. Critics attribute the launch issues to internal problems, such as management and design decisions, casting doubt on the sabotage claims. The saga continues as MindsEye's post-launch turmoil unfolds.

TweakTown•

4 hours ago

3DPrint.com

The Additive Chicken Coop, Part II: Rescoping

The article discusses the second part of the Additive Chicken Coop project, focusing on rescaling the project. It highlights the challenges faced in enabling JavaScript and cookies to continue reading the content. The article provides insights into the technical aspects of the project and the strategies employed to address the issues encountered during the rescaling process.

3DPrint.com•