A Test Generation Procedure Targeting Subcircuits With High Susceptibilities To Aging (Purdue University)

The technical paper from Purdue University discusses a test generation procedure focusing on subcircuits with high susceptibilities to aging. It highlights that delay faults resulting from chip aging can be assessed based on layout or functional workload. The paper introduces a gate-level scan-based test generation method that targets subcircuits prone to aging based on functional switching activity. By augmenting conventional transition fault test sets with tests that improve coverage of these subcircuits, significant enhancements in detecting aging effects are demonstrated. The study emphasizes the importance of detecting delay faults in subcircuits to better understand aging impacts.